Computer Organization and Architecture pdf - Set 02 - ObjectiveBooks

# Practice Test: Question Set - 02

1. In signed-magnitude binary division, if the dividend is (11100) 2 and divisor is (10011) 2 then the result is
(A) (00100) 2
(B) (10100) 2
(C) (11001) 2
(D) (01100) 2

2. Virtual memory consists of
(A) Static RAM
(B) Dynamic RAM
(C) Magnetic memory
(D) None of these

3. In a program using subroutine call instruction, it is necessary
(A) Initialize program counter
(B) Clear the accumulator
(C) Reset the microprocessor
(D) Clear the instruction register

4. If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be
(A) 11 bits
(B) 21 bits
(C) 16 bits
(D) 20 bits

5. A-Flip Flop can be converted into T-Flip Flop by using additional logic circuit
(A) n TQD =•
(B) T D =
(C) D = T . Q n
(D) n TQD =?

6. Logic X-OR operation of (4ACO) H & (B53F) H results
(A) AACB
(B) 0000
(C) FFFF
(D) ABCD

7. Cache memory works on the principle of
(A) Locality of data
(B) Locality of memory
(C) Locality of reference
(D) Locality of reference & memory

8. The main memory in a Personal Computer (PC) is made of
(A) Cache memory
(B) Static RAM
(C) Dynamic Ram
(D) Both (a) and (b)

9. The multiplicand register & multiplier register of a hardware circuit implementing booth’s algorithm have (11101) & (1100). The result shall be
(A) (812) 10
(B) (-12) 10
(C) (12) 10
(D) (-812) 10

10. _________ register keeps tracks of the instructions stored in program stored in memory.
(B) XR (Index Register)
(C) PC (Program Counter)
(D) AC (Accumulator)

11. MIMD stands for
(A) Multiple instruction multiple data
(B) Multiple instruction memory data
(C) Memory instruction multiple data
(D) Multiple information memory data

12. A group of bits that tell the computer to perform a specific operation is known as
(A) Instruction code
(B) Micro-operation
(C) Accumulator
(D) Register

13. The communication between the components in a microcomputer takes place via the address and
(A) I/O bus
(B) Data bus
(D) Control lines

14. An instruction pipeline can be implemented by means of
(A) LIFO buffer
(B) FIFO buffer
(C) Stack
(D) None of the above

15. Data input command is just the opposite of a
(A) Test command
(B) Control command
(C) Data output
(D) Data channel

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