Digital Computer Electronics Questions - Set 09 - ObjectiveBooks
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Digital Computer Electronics Questions - Set 09

Practice Test: Question Set - 09

1. The maximum number of TTL loads that a TTL device can drive reliably over the specified temperature range is
    (A) Fan-out
    (B) Bipolar
    (C) Chip
    (D) Universal logic circuit

2. Conversion of binary number 1011102 to an octal number is
    (A) 358
    (B) 468
    (C) 568
    (D) 508

3. Conversion of an octal number 1438 to hexadecimal number is
    (A) 6316
    (B) 6016
    (C) 5016
    (D) 5716

4. Which of the following TTL subfamily is the fastest?
    (A) Standard TTL
    (B) High-speed TTL
    (C) Schottky TTL
    (D) Low-speed TTL

5. The number of binary bits required to represent a hexadecimal digit is
    (A) 3
    (B) 4
    (C) 6
    (D) 8

6. Conversion of an octal number 1258 to its decimal number is
    (A) 9010
    (B) 8510
    (C) 8710
    (D) 9910

7. Addition of 11012 and 10102 is
    (A) 101012
    (B) 110002
    (C) 110112
    (D) 101112

8. A multiplexer is also known as
    (A) Coder
    (B) Decoder
    (C) Data selector
    (D) Multi-vibrator

9. Division of 1000112 by 1012 is
    (A) 1002
    (B) 1112
    (C) 1012
    (D) 10102

10. What table shows the electrical state of a digital circuit's output for every possible combination of electrical states in the inputs?
    (A) Function table
    (B) Truth table
    (C) Routing table
    (D) ASCII table

11. A ________ is a group of devices that store digital data.
    (A) Circuits
    (B) Register
    (C) Variations
    (D) Bit

12. Express -7 as 16-bit signed binary numbers.
    (A) 0000 0000 0000 0111
    (B) 1000 0000 0000 0111
    (C) 0111 0000 0000 0001
    (D) 0111 0000 0000 0000

13. With a JK master-slave flip-flop the master is cocked when the clock is _______ and the slave is triggered when the clock is _______
    (A) Set, reset
    (B) Race, no change
    (C) High, low
    (D) Set, race

14. Digital design often starts by constructing a _______ table.
    (A) Standard
    (B) Two-stage
    (C) Truth
    (D) Two-dimensional

15. For an input pulse train of clock period T, the delay produced by an n stage shift register is
    (A) (n-1)T
    (B) nT
    (C) (n+1)T
    (D) 2nT

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